The invention is directed to an improved approach for designing, analyzing, and manufacturing integrated circuits.
An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes, for example, interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. After an integrated circuit designer has created the physical design of the circuit, the integrated circuit designer then verifies and optimizes the design using a set of EDA testing and analysis tools.
Rapid developments in the technology and equipment used to manufacture semiconductor ICs have allowed electronics manufacturers to create smaller and more densely packed chips in which the IC components, such as wires, are located very close together. When electrical components are spaced close together, the electrical characteristics or operation of one component may affect the electrical characteristics or operation of its neighboring components, which may negatively affect the timing characteristics of the circuit design. Therefore, one of the key steps in the modern circuit design process is to perform “timing closure”, to ensure that the timing characteristics of the circuit design will meet expected operating requirements.
To perform timing closure, numerous actions are typically taken, including MMMC analysis, where “MMMC” stands for “Multi-Mode Multi-Corner” (which may also be referred to as MCMM or Multi-Corner Multi-Mode). MMMC refers to a design configuration consisting of various functional mode(s) and process corner(s) required to analyze semiconductor design to ensure achieve timing closure. The timing closure process may also include performance of STA (Signoff Timing Analysis) and ECOs (engineering change orders). STA refers to technique of static timing and signal integrity analysis for semiconductor design to measure same be able to run at intended speed (clock frequency) An ECO (engineering change order) refers to incremental netlist changes performed to meet timing closure. Timing closure is the practice that typically includes the above actions for digital circuit designs to ensure that the circuit design meets timing specifications.
As designs move towards lower process technology, timing closure has become a quite challenging. Due to increased number of process variations in lower technologies, a two corner analysis for worst and best PVT (process, voltage, temperature) conditions can result in highly pessimistic analysis. At lower technologies, designs are targeted to close timing at huge number of modes and corner combinations (called views). Different combination of Process/Voltage and Temperature results in exploded number of corners that need to be analyzed for each design. Therefore, the number of process corners has increased exponentially, resulting in many numbers of corners per analysis mode. With the increased number of corners, full chip analysis for all the modes becomes a bottleneck as large numbers of STA runs increasingly affects and extends the design timing closure cycle. Analyzing static timing and signal integrity effects on large numbers of runs (due to the large number of number of MMMC views in modern designs) adds a performance bottleneck to the design system. To address this problem, a circuit designer may decide to avoid performing SI (signal integrity) analysis for all modes to reduce design closure time. Instead of performing this analysis for all modes, the circuit designer may choose place high guard bands (timing derates) to add pessimism that can cover SI effects. This approach may avoid the bottleneck of performing analysis for all corners, but may result in negative effects on the overall QOR (quality of results) of the design.
Therefore, it is clear that there is a need for an improved approach to perform timing closure and optimization.